tensorCUDA.h File Reference

Header file for tensor classes CUDA implementations. Note that for all of these implementations, dynamic memory is not used. All of the memory lives on whichever architecture the class is instantiated on. That is, the "CUDA" suffix indicates nothing about where the memory is, but just indicates that it's in a format that's most suitable for a CUDA implementation. More...

#include <hpp/config.h>
#include <initializer_list>
#include <hpp/tensor.h>
#include <hpp/rotation.h>
#include <hpp/cudaUtils.h>
#include <hpp/hdfUtilsCpp.h>

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Classes
class	hpp::VecCUDA< T, N >
class	hpp::Tensor2CUDA< T, M, N >
class	hpp::Tensor2SymmCUDA< T, N >
class	hpp::Tensor2AsymmCUDA< T, N >
class	hpp::VecCUDA< T, N >
class	hpp::Tensor2CUDA< T, M, N >
class	hpp::Tensor2SymmCUDA< T, N >
class	hpp::Tensor2AsymmCUDA< T, N >
class	hpp::Tensor4CUDA< U, M, N, P, Q >

Namespaces
	hpp

Functions
template<typename T , unsigned int N>
__device__ VecCUDA< T, N >	hpp::operator/ (const VecCUDA< T, N > &inVec, T scalar)
template<typename T >
__device__ VecCUDA< T, 3 >	hpp::cartesianToSpherical (const VecCUDA< T, 3 > &cartVec)
	Uses the "mathematics" convention. More...
template<typename T , unsigned int M, unsigned N>
__host__ __device__ Tensor2CUDA< T, M, N >	hpp::operator- (const Tensor2CUDA< T, M, N > &A, const Tensor2CUDA< T, M, N > &B)
template<typename T , unsigned int M, unsigned N>
__host__ __device__ Tensor2CUDA< T, M, N >	hpp::operator+ (const Tensor2CUDA< T, M, N > &A, const Tensor2CUDA< T, M, N > &B)
template<typename T , unsigned int M, unsigned N>
__host__ __device__ void	hpp::operator+= (Tensor2CUDA< T, M, N > &A, const Tensor2CUDA< T, M, N > &B)
template<typename T , unsigned int M, unsigned N>
__host__ __device__ Tensor2CUDA< T, M, N >	hpp::operator* (const Tensor2CUDA< T, M, N > &A, T scalar)
template<typename T , unsigned int M, unsigned N>
__host__ __device__ Tensor2CUDA< T, M, N >	hpp::operator* (T scalar, const Tensor2CUDA< T, M, N > &A)
template<typename T , unsigned int M, unsigned N>
__host__ __device__ Tensor2CUDA< T, M, N >	hpp::operator/ (const Tensor2CUDA< T, M, N > &A, T scalar)
template<typename T , unsigned int M, unsigned N>
__host__ __device__ void	hpp::operator/= (Tensor2CUDA< T, M, N > &A, T scalar)
template<typename T , unsigned int M, unsigned int N, unsigned int P>
__host__ __device__ Tensor2CUDA< T, M, P >	hpp::operator* (const Tensor2CUDA< T, M, N > &A, const Tensor2CUDA< T, N, P > &B)
template<typename T , unsigned int M, unsigned int N>
__host__ __device__ VecCUDA< T, M >	hpp::operator* (const Tensor2CUDA< T, M, N > &A, const VecCUDA< T, N > &x)
template<typename T , unsigned int M>
__host__ __device__ Tensor2CUDA< T, M, M >	hpp::transformIntoFrame (const Tensor2CUDA< T, M, M > &A, const Tensor2CUDA< T, M, M > &Q)
	Transform tensor \( \mathbf{A} \) into the frame given by the columns of \( \mathbf{Q} \). More...
template<typename T , unsigned int M>
__host__ __device__ Tensor2CUDA< T, M, M >	hpp::transformOutOfFrame (const Tensor2CUDA< T, M, M > &A_star, const Tensor2CUDA< T, M, M > &Q)
	Transform tensor \( \mathbf{A}^* \) out of the frame given by the columns of \( \mathbf{Q} \). More...
template<typename T , unsigned int M>
__host__ __device__ Tensor2CUDA< T, M, M >	hpp::transformIntoFrame (const Tensor2AsymmCUDA< T, M > &A, const Tensor2CUDA< T, M, M > &Q)
template<typename T , unsigned int M>
__host__ __device__ Tensor2CUDA< T, M, M >	hpp::transformOutOfFrame (const Tensor2AsymmCUDA< T, M > &A_star, const Tensor2CUDA< T, M, M > &Q)
template<typename T >
__device__ Tensor2CUDA< T, 3, 3 >	hpp::EulerZXZRotationMatrixCUDA (T alpha, T beta, T gamma)
template<typename T , unsigned int M, unsigned int N>
std::ostream &	hpp::operator<< (std::ostream &out, const Tensor2CUDA< T, M, N > &A)
template<typename T , unsigned int M, unsigned N>
__device__ Tensor2CUDA< T, M, N >	hpp::warpReduceSumTensor2 (Tensor2CUDA< T, M, N > A)
template<typename T , unsigned int M, unsigned N>
__device__ Tensor2CUDA< T, M, N >	hpp::blockReduceSumTensor2 (Tensor2CUDA< T, M, N > val)
template<typename T , unsigned int M, unsigned N>
__global__ void	hpp::BLOCK_REDUCE_KEPLER_TENSOR2 (Tensor2CUDA< T, M, N > *in, Tensor2CUDA< T, M, N > *out, int nTerms)
template<typename T , unsigned int M, unsigned int N>
__device__ EulerAngles< T >	hpp::getEulerZXZAngles (const Tensor2CUDA< T, M, N > &R)
	Coresponds to the ZXZ Proper Euler Angles. More...
template<typename T , unsigned int N>
__host__ __device__ Tensor2SymmCUDA< T, N >	hpp::operator- (const Tensor2SymmCUDA< T, N > &A, const Tensor2SymmCUDA< T, N > &B)
template<typename T , unsigned int N>
__host__ __device__ Tensor2SymmCUDA< T, N >	hpp::operator+ (const Tensor2SymmCUDA< T, N > &A, const Tensor2SymmCUDA< T, N > &B)
template<typename T , unsigned int N, unsigned int P>
__host__ __device__ Tensor2CUDA< T, N, P >	hpp::operator* (const Tensor2SymmCUDA< T, N > &A, const Tensor2CUDA< T, N, P > &B)
template<typename T , unsigned int N>
__host__ __device__ Tensor2AsymmCUDA< T, N >	hpp::operator- (const Tensor2AsymmCUDA< T, N > &A, const Tensor2AsymmCUDA< T, N > &B)
template<typename T , unsigned int N>
__host__ __device__ Tensor2CUDA< T, N, N >	hpp::operator- (const Tensor2AsymmCUDA< T, N > &A, const Tensor2CUDA< T, N, N > &B)
template<typename T , unsigned int N>
__host__ __device__ Tensor2AsymmCUDA< T, N >	hpp::operator+ (const Tensor2AsymmCUDA< T, N > &A, const Tensor2AsymmCUDA< T, N > &B)
template<typename T , unsigned int N, unsigned int P>
__host__ __device__ Tensor2CUDA< T, N, P >	hpp::operator* (const Tensor2AsymmCUDA< T, N > &A, const Tensor2CUDA< T, N, P > &B)
template<typename T , unsigned int N, unsigned int P>
__host__ __device__ Tensor2CUDA< T, N, P >	hpp::operator* (const Tensor2CUDA< T, N, P > &A, const Tensor2AsymmCUDA< T, P > &B)

Detailed Description

Header file for tensor classes CUDA implementations. Note that for all of these implementations, dynamic memory is not used. All of the memory lives on whichever architecture the class is instantiated on. That is, the "CUDA" suffix indicates nothing about where the memory is, but just indicates that it's in a format that's most suitable for a CUDA implementation.

An anti-symmetric second order tensor.

A symmetric second order tensor.

Author

Michael Malahe

The underlying storage is row major. For example, for a 4x4 symmetric tensor there will be a total of (4*(4+1))/2 = 10 elements stored. Those elements are ordered in memory as: [T(0,0),T(0,1),T(0,2),T(0,3),T(1,1),T(1,2),T(1,3),T(2,2),T(2,3),T(3,3)].

The underlying storage is row major. For example, for a 4x4 anti-symmetric tensor there will be a total of (4*(4-1))/2 = 6 elements stored. Those elements are ordered in memory as: [T(0,1),T(0,2),T(0,3),T(1,2),T(1,3),T(2,3)].